課程介紹
This course is designed to give you a comprehensive coverage of the VLSI architectures for digital signal processing. The main theme of the course is to design efficient VLSI architectures for computing algorithms frequently encountered in DSP systems. In other words, this course will teach you how to map DSP algorithms onto VLSI. You will learn the basic properties of VLSI algorithms and their relations with the VLSI implementation. You will also learn a lot of algorithm transformation and architecture design techniques to improve your design. A systematic introduction to this design process will be elaborated. Fundamental knowledge toward DSP, computer architecture and parallel processing is preferred but not a prerequisite. The detailed contents of this course include

introduction to VLSI digital signal processing

review of DSP algorithms & algorithm representations

iteration bound

pipelining and parallel processing

retiming

unfolding

folding

mapping algorithms onto array structures

FIR filter design example

pipelined and parallel recursive and adaptive filters

From algorithm to bit-true design

Circuit design techniques

QR factorization design example

教科書:
“VLSI Digital Signal Processing Systems – Design and Implementation,” by Keshab Parhi, John Wiley & Sons, 1999
教學進度:

The grading of this course is based on homeworks, exam and term project. There are two types of homeworks, that is,

regular - this is the ordinary written homework, mostly from the problems of the textbook

simulation - you will be asked to use Verilog to simulate and verify small design

There will be mid-term and final exams. For the term project, you will be assigned a DSP module and derive its VLSI design using the techniques learned from the class for optimization. You should give a performance evaluation and include simulation result of your design.

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