課程介紹

This course addresses 2 major aspects of the hardware description language (HDL). The first one is digital design using hardware description language. The second one is logic synthesis. In addition, a brief review on logic design will be given at the beginning of the semester. You are expected to achieve the following capabilities after taking this course

            - proficiency in digital designs using HDL

            - understanding how the logic synthesis works

            - correctly writing the synthesizable code and interpreting the synthesis result

教科書:
Samir Palnitkar, "Verilog HDL – A Guide to Digital Design and Synthesis," 2nd edition, Prentice Hall, 2005
教學進度:

Part A. Digital design using HDL (12 weeks)

            - Overview of digital design with HDL

            - Review of logic design basics

            - Hierrachical modeling and Basic concepts

            - language basics of Verilog

            - Data flow modeling

            - Behavioral Modeling

            - Design examples

            - Advanced coding techniques

            - Timing modeling and Verification

            - Case studies

Part B. Logic synthesis (3 weeks)

            - Synthesizable coding

            - Logic synthesis flow

            - Logic synthesis constraints

            - logic synthesis report

Part C. Verilog simulation tool (1 week)

            - ModelSim

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